News Briefing
  • Global memory chip manufacturer leader Samsung Electronics aims to increase its production of High Bandwidth Memory (HBM) chips nearly threefold this year to seize the leading position in the AI memory chip market. Additionally, SK Hynix, the current leader in the HBM market, has announced plans to invest $3.87 billion to build an HBM packaging plant in Indiana, USA, with operations expected to commence in the second half of 2028.
Impact analysis
  • In the most advanced processor architectures such as AI and HPC, High Bandwidth Memory (HBM) technology is widely adopted, as seen in products like NVIDIA's H100/H200 and B100/B200 series, as well as AMD's MI300 series. This is because the AI era emphasizes computational power, and to enhance computing power, performance must be improved simultaneously in the three aspects of data calculation, transmission, and storage. HBM is the optimal choice for increasing memory data transfer rates. By stacking multiple DRAMs in a 3D configuration, HBM achieves ultra-high speeds, with each memory bandwidth adding up to achieve speeds of up to 1TB/s, meeting the demands of computational power. The next-generation HBM3e can further increase bandwidth to 8Gbps, delivering higher performance for new AI accelerator chips from 2024 to 2025.
  • Currently, only three companies globally have the capability to produce HBM: SK Hynix, Samsung Electronics, and Micron Technology. Due to the higher unit price and lucrative profits of HBM, it has attracted significant capital expenditure investments. According to TrendForce's estimation, by the end of 2024, the overall DRAM industry plans to have a production capacity of approximately 250K/m for HBM TSV, accounting for about 14% of the total DRAM production capacity (approximately 1,800K/m). In 2023, the HBM production value accounted for approximately 8.4% of the overall DRAM industry, and it is expected to expand to 20.1% by the end of 2024, with a significant growth rate. Meanwhile, the development of HBM has also influenced the design of ABF substrates. AI chips are packaged together with HBM and GPU through CoWoS + 2.5D packaging technology to increase transistor density. For packaging substrates, this will require larger board areas and more layers to ensure wiring and interconnection capabilities, which ultimately contribute to improving capacity utilization and product prices.